Description
Remote is hiring a remote Front End Design Engineer (contract, mid level). The role is open to people living in any country. The employer has not published a salary. Working hours: Minimum 40 hours per week with daily overlap of 4 hours with PST.. You apply directly on the employer's site.
About the role
Build hardware-engineering training data and benchmarks for frontier AI labs. As a front-end design engineer, you turn real RTL work into tasks that measure how well AI models design hardware: each task has a specification, a starting design, a reference solution, and the tests that grade it. In this track, you will build the design tasks themselves: RTL design, bugfix, and PPA (power, performance, area) problems on real IP, graded with the same simulation, synthesis, and equivalence-checking flows used to tape out chips. This is fundamentally a front-end design role: you write RTL, take it through commercial and open-source synthesis, and can explain why the area, timing, and power came out the way they did. The artifacts you produce become the ground truth these models learn from and are measured against. Your specifications, reference solutions, and tests shape what the next generation of models learns about digital design, so each one must hold up to the same scrutiny as a design going to tape-out.
What you'll do
- Author design tasks: Turn real IP into precise RTL design, bug-fix, and PPA‑optimization tasks: the specification, the starting point, and a reference solution that meets every requirement.
- Set the PPA bar: Run commercial and open-source synthesis to establish area, power, and timing baselines, and set targets that reward real engineering rather than lucky tool settings.
- Prove correctness: Build the hidden tests and equivalence checks a solution must pass, so no design can trade away function for a better number.
- Break your own tasks: Attack each task the way a model would (removed logic, constraint loopholes, untested corners) and close the gaps before it ships.
Experience
Experience: 3+ years of front-end digital design on ASIC or FPGA projects, from RTL through synthesis. • RTL design: Fluent Verilog / SystemVerilog: microarchitecture, datapaths, FSMs, pipelines, FIFOs, clock-domain crossings, and clock gating. • Synthesis and PPA: Hands-on logic synthesis with timing constraints. You read timing and quality-of-results reports and know which RTL or constraint change moves area, timing, or power. • Commercial EDA: Hands-on commercial synthesis in industry, research, or project work: Cadence Genus, Synopsys Design Compiler / Fusion Compiler, or, for FPGA targets, AMD Vivado (including Vitis HLS flows). • Open-source EDA: Hands-on open-source synthesis with Yosys, directly or through an OpenLane / LibreLane flow, and open-source simulation with Icarus Verilog or Verilator, directly or under cocotb. • Verification: Self-checking testbenches in cocotb (Python) or SystemVerilog, and waveform-level debug. • Scripting: Python and Tcl for flow automation; at home in Linux, Git, and Docker‑based environments. This is how every task runs.
Skills
- Python
Who can apply
This job is open to people living in any country. There are no location restrictions. Working hours: Minimum 40 hours per week with daily overlap of 4 hours with PST..
How to apply
- 1Check that you live where this job hires (any country) and can work minimum 40 hours per week with daily overlap of 4 hours with pst..
- 2Click “Apply Now” to open Remote's application page.
- 3Apply soon: listings close when the role is filled.
Interested in this role?
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